CSIS3600.cpp

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/*
                    GNU GENERAL PUBLIC LICENSE
                       Version 2, June 1991

 Copyright (C) 1989, 1991 Free Software Foundation, Inc.
                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 Everyone is permitted to copy and distribute verbatim copies
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*/


#include <config.h>

#include "CSIS3600.h"



#ifndef __VMEMODULE_H
#include <VmeModule.h>
#endif

#ifdef HAVE_STD_NAMESPACE
using namespace std;
#endif

// Structure of the module registers (offsets).

#define CSR              0x000  // Control status register offset.
#define IDIRQ            0x004  // Identification and IRQ register.
#define FCLEARWIN        0x008  // Fast clear window.
#define OPFREQ           0x00c  // Ouput pulse frequency generator.
#define WRITEFIFO        0x010  // Write to fifo in test mode.
#define CLEARFIFO        0x020  // KEY: Clear the FIFO.
#define NEXTCLOCK        0x024  // KEY: VME Next clock.
#define ENABLENEXTCLOCK  0x028  // KEY: Enable next clock logic.
#define DISABLENEXTCLOCK 0x02c  // KEY: Disable next clock logic.
#define ENABLEFCLEAR     0x050  // KEY: Enable fast clear.
#define DISABLEFCLEAR    0x054  // KEY: Disable fast clear.
#define RESET            0x060  // KEY: Reset the module.
#define PULSEOUT         0x068  // KEY: Generate an output pulse.
#define CBLTSETUP        0x080  // CBLT setup register.
#define FIFO             0x100  // FIFO (data).

// The CSR is both a status and a control register.  The
// bit structures below (assuming that bits are defined low to high'
//e the structure of these registers..

struct StatusRegister {
  unsigned LedOn:1;             
  unsigned TestingFIFO:1;       
  unsigned OutputMode:2;        


  unsigned OutputPulseEnabled:1; 
  unsigned isPipelined:1;       
  unsigned isBroadcastOn:1;     
  unsigned isBCastController:1; 

  unsigned FIFOEmpty:1;         
  unsigned FIFOAlmostEmpty:1;   
  unsigned FIFOHalfFull:1;      
  unsigned FIFOAlmostFull:1;    

  unsigned FIFOFull:1;          
  unsigned Unused1:1;           
  unsigned FastClearEnabled:1;  
  unsigned isEnableNext:1;      

  unsigned isExternalNext:1;    
  unsigned isExternalClear:1;   
  unsigned isLatchGate:1;       
  unsigned isCoincidenceMode:1; 

  unsigned isEnableVMEIrq0:1;   
  unsigned isEnableVMEIrq1:1;   
  unsigned isEnableVMEIrq2:1;
  unsigned isEnableVMEIrq3:1;

  unsigned Unused2:1;           
  unsigned Unused3:1;           
  unsigned InternalVMEIRQ:1;    
  unsigned VMEIRQ:1;            

  unsigned VMEIRQ0:1;           
  unsigned VMEIRQ1:1;           
  unsigned VMEIRQ2:1;           
  unsigned VMEIRQ3:1;           
};

struct ControlRegister {
  unsigned SetLEDOn:1;          
  unsigned SetFIFOTest:1;       
  unsigned SetModeBit0:1;       
  unsigned SetModeBit1:1;       

  unsigned EnableOutputPulses:1; 
  unsigned EnablePipeline:1;    
  unsigned EnableBroadcast:1;   
  unsigned EnableBcastController:1; 

  unsigned ClearLEDOn:1;        
  unsigned ClearFIFOTest:1;     
  unsigned ClearModeBit0:1;     
  unsigned ClearModeBit1:1;     

  unsigned DisableOutputPulses:1; 
  unsigned DisablePipeline:1;   
  unsigned DisableBroadcast:1;  
  unsigned DisableBcastController:1; 

  unsigned EnableExternalNext:1; 
  unsigned EnableExternalClear:1; 
  unsigned SetLatchGate:1;      
  unsigned SetCoincidenceMode:1; 

  unsigned EnableIRQ0:1;        
  unsigned EnableIRQ1:1;
  unsigned EnableIRQ2:1;
  unsigned EnableIRQ3:1;

  unsigned DisableExternalNext:1; 
  unsigned DisableExternalClear:1; 
  unsigned ClearLatchGate:1;    
  unsigned ClearCoincidenceMode:1; 

  unsigned DisableIRQ0:1;       
  unsigned DisableIRQ1:1;
  unsigned DisableIRQ2:1;
  unsigned DisableIRQ3:1;

};

struct IdIrq {
  unsigned IRQVector:8;         

  unsigned IPL:3;               
  unsigned IRQEnable:1;         

  unsigned Version:4;           

  unsigned ModuleId:16;         

};


//
//  The following union definitions make it easier to deal with
//  the bit-wise/long wise duality of registers:
//
union IdRegister {              // ID IRQ register...
  IdIrq         bits;
  unsigned long l;
};


union StatReg {
  StatusRegister  bits;
  unsigned long   l;
};

union CtlReg {
  ControlRegister bits;
  unsigned long   l;
};

// The register unions above have a structure that is identical
// in order to allow us to do the following little macro games:

#define SetBit(reg, field, value) reg.bits.field  = value
#define GetBit(reg, field)        reg.bits.field
#define Zero(reg)                 reg.l           = 0
#define Long(reg)                 reg.l


static const unsigned int ModuleLength(0x200); 

CSIS3600::CSIS3600(unsigned long base, int crate) throw (string) :
  CModule32(base, ModuleLength, crate)
{
  IdRegister id;


  unsigned long csr = peek(CSR); // Sometimes needed for good->bad
                                // module construction to shake up
                                // the bus bits a bit.

  Long(id) = peek(IDIRQ);

  if(GetBit(id,ModuleId) != 0x3600) {
    ThrowString("CSIS3600::CSIS3600",
                "No 3600 at this base address");
  }
  Reset();                      // Reset the module.
}
CSIS3600::~CSIS3600()
{
}
void
CSIS3600::LightLed() const
{

  CtlReg csr;

  Zero(csr);
  SetBit(csr, SetLEDOn, 1);

  poke(Long(csr), CSR);

  
}
void
CSIS3600::ClearLed() const
{

  CtlReg csr;

  Zero(csr);
  SetBit(csr, ClearLEDOn, 1);


  poke(Long(csr), CSR);

  
}
bool
CSIS3600::isLedLit() const
{
  StatReg sr;

  Long(sr) = peek(CSR);
  return (GetBit(sr,LedOn) == 1);
}
void
CSIS3600::SetLatchMode() const 
{

  CtlReg cr;

  Zero(cr);
  SetBit(cr,ClearCoincidenceMode, 1);

  poke(Long(cr), CSR);
}
void
CSIS3600::SetCoincidenceMode() const
{

  CtlReg cr;

  Zero(cr);
  SetBit(cr,SetCoincidenceMode,1);

  poke(Long(cr), CSR);
}
bool
CSIS3600::isLatchMode() const
{
  StatReg sr;

  Long(sr) = peek(CSR);

  return (GetBit(sr,isCoincidenceMode) == 0);
}
void
CSIS3600::Reset()
{
  Key(RESET);
  m_nFastClearWindow = 220;     // Default initial fast clear window.
}
void
CSIS3600::EnableExternalNext() const
{
  CtlReg cr;
  Zero(cr);
  SetBit(cr, EnableExternalNext, 1);
  poke(Long(cr), CSR);
}
void 
CSIS3600::DisableExternalNext() const
{
  CtlReg cr;
  Zero(cr);
  SetBit(cr, DisableExternalNext, 1);
  poke(Long(cr), CSR);
}
bool
CSIS3600::ExternalNextEnabled() const
{
  StatReg sr;
  Long(sr) = peek(CSR);
  return (GetBit(sr, isExternalNext) == 1);
}
void
CSIS3600::EnableExternalClear() const
{
  CtlReg cr;
  Zero(cr);
  SetBit(cr,EnableExternalClear ,1);
  poke(Long(cr), CSR);
    
}
void 
CSIS3600:: DisableExternalClear() const
{
  CtlReg cr;
  Zero(cr);
  SetBit(cr, DisableExternalClear, 1);
  poke(Long(cr), CSR);
}
bool
CSIS3600::ExternalClearEnabled() const
{
  StatReg sr;
  Long(sr) = peek(CSR);
  return (GetBit(sr, isExternalClear) == 1);
}
void
CSIS3600::SetFastClearWindow(int ns)
{
  m_nFastClearWindow = ns;
  ns += 50;                     // This ensures rounding.
  unsigned int reg =ns;
  reg = (reg - 120)/100 -1;
  if(reg > 0xff) {
    ThrowString("CSIS3600::SetFastClearWidow",
                "Fast clear window range is [220, 25720]ns");
  }

  poke(reg, FCLEARWIN);
}
int
CSIS3600::GetFastClearWindow() const
{
  return m_nFastClearWindow;
}
void
CSIS3600::StartLatch() const
{
  CtlReg cr;
  Zero(cr);
  SetBit(cr, SetLatchGate,1);

  poke(Long(cr), CSR);
}
void
CSIS3600::EndLatch() const
{
  CtlReg cr;
  Zero(cr);
  SetBit(cr, ClearLatchGate,1);

  poke(Long(cr), CSR);
}
bool
CSIS3600::DataReady()  const
{
  StatReg  sr;

  Long(sr) = peek(CSR);

  return ((GetBit(sr, FIFOEmpty)) == 0);
}
void
CSIS3600::Enable() const
{
  Key(ENABLENEXTCLOCK);
}
void
CSIS3600::Disable() const
{
  Key(DISABLENEXTCLOCK);
}
void
CSIS3600::Clock() const
{
  Key(NEXTCLOCK);
}
void
CSIS3600::ClearData()  const
{
  Key(CLEARFIFO);
}
unsigned long
CSIS3600::Read() const throw (string)
{
  if(DataReady()) {
    return peek(FIFO);
  }
  else {
    ThrowString("CSIS3600::Read",
                "No data present");
  }
}
unsigned int
CSIS3600::Read(void* pBuffer, 
                     int nLongs) const
{
  unsigned long* p = (unsigned long*)pBuffer;
  unsigned int   n = 0;

  // This code assumes that a throw/catch is relatively expensive.

  while(DataReady() && nLongs) {
    *p++ = Read();
    n++;
    nLongs--;
  }
  return n;
}

---