sis3316

Specifies the VME base address of the module.

Specifies the clock frequency or source for the digitizers valid values are fp which selects the front panel input for the clock, and 250MHz, 125MHz, 50Mhz, 25MHz or 12.5MHz. Note the internal module parameters for the 12.5MHz clock have been guessed from the parameter patterns for the other clock frequencies. Please advise if this was done incorrectly.

If you use the front panel clock (fp), you must supply the correct value for the -adcdelaytap or else the data read from the module will be corrupted. See the -adcdelaytap below.

Specifies the top 7 bits of the id word in the event header. The remaining bits are set from the ADC group and ADC channel within the group to fully identify the channel. The value configured here allows you to distinguish between the modules in a multi-module setup.

Each element of the list must be an integer in the range [0, 65535] and specfies the pretrigger value for the corresponding ADC group (e.g. element 0 for channels 0-3 etc.).

Each element of the list must be an positive integer in the range [0-65535] and specifies the number of samples that will be acquired in the four ADCs in the corresponding group of four ADCs.

Each element of the list must be a boolean which is true if the corresponding digitizer channel is enabled to store data. List elmeent 0 enables or disables channel 0 and so on.

Sets the attenuation circuits in each of the ADC channels to define the full scale range for the channel. Each of the 16 elements of the list can be one of: 5V, 2V, or 1.9V. The range for each channel can be set independently. If not specified, 5V is selected for all channels.

Each element of the list determines the input impedence. A true selects 1KOhm termination. false, the default, selects 50Ohm input termination. The default is a 16 element list of false specifying 50Ohm termination for all channels. The input impedance an be selected independently for each channel.

Refer to sections 2.5.3 and 6.39 of the manual. The timing of data transfer from ADC to its associated FPGA depends on the digitization clock frequency. This timing is set programmatically via delay line taps. If you select an internal, programmable clock with the clock, the software determines the correct values for the input tap delay registers and this option is ignored.

Obviously, with an external, clock (fp) the software cannot know the correct values for these delays. you must therefore use -adcdelaytap to tell the software how to set this value. Refer to the tabls in section 6.39 of the manual. In your value for this parameter, you must not set the channel select bits but you might need to set the 1/2 clock delay bit. For example, with a 100MHz input clock on a 250MHz ADC module, you must set the value 0x1020 where 0x20 is the delay value and 0x1000 is the 1/2 sample delay bit. For an external 125MHz clock, you must use 0x50, as that clock frequency does not require an additional 1/2 sample delay.

	WARNING
	Using a front panel, external clock with an incorrect value for -adcdelaytap will result in corrupted trace data.

Sets the averaging decimation for each channel. You can use decimation to effectively lower the sampling clock frequency. If decimation is enabled, each sample in the returned waveform is the average of several consecutive samples. Valid values for each list element are: off, 2, 4, 8, 16, 32, 64, 128, 256, 512

off which is the default value for all channes if this is not specified disables decimation; each waveform value is one sample from the ADC. The other values specify the number of adc samples that are averaged to produce the trace in the event. Note that this averaging is not done with a sliding window; if you select 2, for example the first trace element will be the average of samples 0, 1 and the second the average of 2, 3.