mdpp32scp

Configures the base address of the module.

Identifying value the module will put into the data stream to identify the module it came from. This must be in the rang 0-255 (8 bits) and should be unique across modules. If not configured, this defaults to 0.

The interrupt priority level at which the module will interrupt. If this is zero, as it is if not configured, interrupts are disabled for the module.

If the module interrupts are enabled/used, this is the status id the module wilil assert when it interrupts.

IF interrupts are used for this module, the module will interrupt when it has at least this this number of 32 bit words buffered in its FIFO. If not configured, this defaults to 1 which means the interrupt will happen as the first event is buffered.

Specifies the maximum number of words that can be read from the FIFO. If the FIFO has more words availalble the module will terminate the transfer.

Determines when an interrupt happens if enalbed. If event, the default if not configured, the module interrupts when the event threshold is met (-irqeventthreshold), if data, when the -irqdatathreshold is met.

Sets the event threshold to use when interrupts are enabled and the -irqsourceK is set to event. If not configured, the default is 3.

If not configured, this defaults to 32bit. The only effect configuring this has on acquisition is that if 64bit is selected, the data read will be padded out to the next 64 bit boundary if needed with a "FIll dummy word" as described in the QDC Firmware manual

IF not set, this defaults to 0x0b. See The MDPP-16 manual. This value specifies the value for the register at base + 0x6036 - the multi-event mode register.

Determines what the module will put in the end of event trailer word. By default, if not configured, timestamp is selected. If extended-timestamp is selected, the module will add an additional 16 high order bits of timestamp. See the FIFO format in the QDC Firmware manual for more details.

Selects the time resolution for the computed tdc. If not configured, defaults to 24ps.

The value to store in register at 0x6044, the output format register. Only the bottom two bits can be selected, and the default value is 3 which is the power up value of that register.

The ADC resolution selected (register 0x6046). If not configured this defaults to 64k

Start of the window of interest relative to the trigger. See register 0x6050 in the The MDPP-16 manual. If not configured, this defaults to 0x3fbe. This is in steps of 1.56ns. The default value is about 81ns before the trigger.

Width of the window of interest. If not configured, the default is 0x80 which represents a window width of about 200ns.

If true, then only the first hit found in the region of interest is transmitted in the event. If not configured, this is true by default.

Turns on or off the test pulser. This is off if not explicitly configured to be enabled

If the -testpulser is enabled, this will be the amplitude of the test pulser pulses. See register 0x6072 of the The MDPP-16 manual.

Defines the trigger. The region of interest in the input signal is then defined by -windowstart and -windowwidth relative to when this trigger happens. See register 0x6058 in the The MDPP-16 manual. Only the bottom 10 bits of the value are used. By default, 0 is written into this register if not configured.

Defines the signal that will be presented on the trigger output NIM out. See register 0x605a. See The MDPP-16 manual for more information. Note that only the bottom 10 bits of the value are used. If not configured, 0 is written to this register

Enables or disables the monitor output. See, however, -monitorch and -setwave configuration options to select what the monitor output show. If not configured, this configures to off by default.

Selects the channel to use for the monitor outputs. The actual waveform monitored in mon0 and mon1 will depend on the value of -setwave. To see anything at those outputs, also requires configuring -monitoron to on

Determines which waveform in the FPGA processing of the waveform is presented for the channel selected by -monitorch on the Mon1 and Mon2 outputs. See the discussion of the monitor outputs in the description of the monitor outputs The MDPP-16 manual for information about what the actual values of this option will select. If not configured, 0 is programmed, selecting the preamplifier output and trigger.

8 element list of the differentiation and integration times for four channel groups (quads). The legal values are 1-125 in steps of 12.5ns. If not explicitly programmed, this defaults to 8 elements of 20.

List of 32 pole zero corrections, one per channel. Legal list element values are 64-65535. These represent signal decay times between 0.8usec and 800usec. The value 65535 (0xffff) represents and infinite decay time. If not explicitly programmed, this parameter defaults to 32 0xffff elements.

The gain values for each quad of channels. The actual gain is the value multiplied by 100. Legal values are 1-2500. If not configured, all quads are programmed with a gain register value of 200 (gain of 20000).

List of individual channel thresholds. This value is between 0 a 65535. 65535 corresponds to full scale. If not programmed all 32 channels are given a threshold value of 2000.

The shaping time values for each quad of channels. This should be the signal FWHM time with values from 8--1000 representing 100ns to 12.5usec. If not configured, all quads will be progrmmed with 200.

Provides the baseline restoration parameter for each quad. Legal values are: 0 - off, 1 - 4x shaping time, 2 8x shaping time and 3 - 1 x shaping time. If not explicitly configured all quads are programmed with 2.

Sets the signal rise time for each quad. For fast detectors, this shoulid be zero (the default for all quads if not configured). Legal values are 0-0x7f and represent 15ns to 1.6usec.

The reset time for each channel quad for the preamp. If not programmed, this defaults to 8 elements of 32 which is normally sufficient. Values can range from 0-0x3ff and the time is in 12.5ns steps.

This is a 14 element list. The first element of the list are the channel mask for IRQ1 channels 0-15 and the second list element the channel mask for IRQ1 for channels 16-31 and so on.