sis3300

Defines the base address of the board. This must match the value selected by the rotary switche in conjunction with the J1 jumper which should be set to enable A32, disble GIO and disable VIPA when used at the FRIB.

See section 3 of the Module's manual for information about setting the base address in the module's hardware.

Sets the source of the digizizer clock. This defaults to 100Mhz. external expects a symmetric clock on LEMO or ECL connector clock input. random digitizes every 100MHz but only stores a sample when the externa clock input pulses. hira only digitizes on the falling edge of the external clock and can tolerate a highly asymmetric clock as will come from the XLM attached to the Wash U Chip boards.

Determines when the module acquires samples. In start, the default, samples will start being acquired on the leading edge of Lemo input 3. Sampling will continue until the programmed number of -samples have been acquired. In this mode you can either delay the readout the appropriate amount or use the rising edge of LEMO output 2 to know when sampling is done and trigger the event from it. In stop mode, the module is always sampling into its memory, treating it like a circular buffer. The stop input terminates sampling. In gate mode, sampling begins on the leading edge of the gate and ends on its trailing edge.

If disabled, the default, no start delay is performed. If an integer value, in the range [0-65535], the external start is delayed by num-clocks+2 samples clocks. This allows for pre-triggering.

Same as for -startdelay but optionally delays the stop. See section 4.8 of the Module's manual for more on start and stop delay modes.

In start and stop mode, this represents the number of samples the module will pass into the event. The default is 128K

The module is capable of generating a trigger output when the input signal passes threshold values for each of the inputs. This allows the module to operate in self-triggered mode by, e.g. connecting the trigger out to the Start input and specifying the module's mode to be start These 8 booleans specify the direction of threshold crossing that generates the trigger for each channel. For each channel, if that channel's list element is true triggers will be generated when the signal passes below its threshold value. IF false triggers are generated when the signal passes above the threshold. The default is lrepeat 8 false setting all channels to require the signal pass above the threshold to generate the trigger.

Provides the threshold values for each of the channels. THis must be a value in the range [0-0x3fff] and defaults to lrepeat 8 false setting all thresholds to the maximum allowed value.

Channels are organized as four two channel groups. This option sets the number of clocks that a signal must be below the threshold Value in that group if the channel's threholdslt is true to generate a trigger. This is useful if the signal is noisy to prevent false triggers. The default is lrepeat 4 0 which will trigger as soon as the signal passes below the threshold

See -mingttime this performs the same function for channels that have -thresholdslt false, setting the time the signal must be above threshold to fire the trigger. This defaults to lrepeat 4 0

If non-zero specifes the number of clocks the auto trigger is held for. The default is lrepeat 4 0.

Provides for selective enable/disable of each 2 channel group. The default is lrepeat 4 true which enables all groups.

Specifies the value of a header placed in the data by the readoutlist. The header value is a marker. Recall that MVLC markers are 32 bits not 16 bits. The default value is 0xfadcfadc This differs from the VMUSB which only uses 16 markers and has a defalut value of 0xfadc

Defines the value of the marker that is inserted at the end of readout. This defaults to 0xffffffff Recall that the MVLC markers are 32 bits wide where the VMUSB markers are 16 bits wide. This differs, therefore from the default for the VMUSB which is 0xffff