sis3316 create name ?option value ...?
sis3316 config name option value ?...?
sis3316 cget name ?option?
The sis3316 supports adding SIS3316 digitizers to the event data. While this module is capable of a lot of digital signal analysis (PHA, PSD, digital CFD based timing), and channel based triggering, we only support waveform capture for externally triggered events.
The module channnels can be individually enabled, and only enabled channels will contribute data. See section 4.6 of the manual. That page shows the data each individual, enabled channel will contribute to the event. Note that all format bits described ont that page are zero and MAW test data are disabled. Thus, for each enabled channel, you can expect a 3 longword header folowed by the captured waveform, with two samples packed into each 32 bit value.
To understand the choices of the configuration option values, it's important to know that groups of four channels are controlled by an ADC FPGA. Some parameters are common to the ADC FPGA that controls its channels. THe Tcl lrepeat can be used to generate these lists if all groups should have the ame value. See https://www.tcl-lang.org/man/tcl8.6/TclCmd/lrepeat.htm
The configuration options for the sis3316 command/module are as follows:
-base base-address Specifies the module base address. Not the program $DAQROOT/sis3316/inventory will probe the VME bus and list the SIS3316 modules plugged in along with their base addresses and a few other things.
-clock clock-source Specifies the sampling clock. This can defaults to 125MHz It can be one of:
fp - clock is from the front panel.
250MHz- clock is 250MHz. Note that not all SIS3316 modules are 250MHz capable.
125MHz
50MHz
25MHz
-samples four-element-listSets the number of samples that will be acquired for each of the four ADC FPGAs. Thererfore, the parameter for this option is a four element Tcl list that provides the number of samples for each FPGA. The default value is the equivalent of [lrepeat 4 65535]. 65535 is also the largest number of samples that can be specified in any single channel group.
-id integer Value between 0 and 127. This will become the top bits of the id in the data from the digitizer. The bottom four bits will identify the channel (two bits for ADCFPGA number and two bits for the channel within the ADC FPGA). Default value is 0.
-pretrigger four-element-list The pretrigger in units of samples for each for each of the ADC FPGAs. THis defaults to 0.
-enable 16-elment-boolean-list Each element of the list, when true, enables a channel, when false, disables it. the first element is channel 0 and so on.
-range |5V | 2V | 1.2VSets the ADC input range to one of the above allowed values.
-term1Kohm booleanIf true, the input terminations are set to 1KOhm, if false, 50Ohm.
-adcdelaytap value
The SIS3316 timings for internal data transfer depend on the sampling clock.
If the front panel clock is seleted (--clock fp),
The user must supply the correct value for the delay line tap selection.
Refer to section 6.39 of the manual which includes a table of delay line settings.
If a half sample delay is required, your value must have bit 0x1000
set. E.g. the correct value for an external 100MHz clock and a 250MHz digitizer is
0x1020.
If you get this delay value wrong, your data will be corrupted.
-decimations 16-element-listThe value of this parameter is a list of 16 decimation selectors, one for each ADC channel. The legal values for each element are: off, 2, 4, 8, 16, 32, 64, 128, 256, 512. off disables decimation for that channel. Other values specify the decimation factor (the SIS3316 does decimation by averaging). So, for example, the value 4 means that each sample value in the event, represents the average of four consecutive ADC sample values for that channel. The default value is a list of 16 off values.
Decimation can be used to get effective clock speeds (on a per channel basis) that are slower than the actual selected clock. For example selecting a decimation of 4 with a clock selection of 50MHz produces an effective clock of 12.5MHz which is not directly supported by the code.