module create name sis3300 ?options...?
name config option1 value1 ?....?
name cget ?pattern?
name help
Provides support for the SIS3300 and SIS3301 flash ADC modules. Note that this module can create a very large contribution to the event size depending on the size of the waveform acquired.
This module is a little complex so refer to the manual for detailed information about the meanings of parameters if you don't understand them.
base base-addressSets the base address for the module. This must match the base address implied by the rotary switches.
crate crate-noSets the number of the VME crate in which the module is inserted. This defaults to 0 which is suitable for a single crate system.
startdelay delay-ticks
When using the external start, a start signal is
internally delayed by delay-ticks+2 clocks
before being presented to the internal circuitry.
stopdelay delay-ticks
When using the external stop input, this provides a
delay of delay-ticks+2 clocks
before the stop is presented to the circuitry.
gate booleanEnables or disables gate mode for the module.
wrap booleanEnables or disables wrap mode for the module's acquisition memory management.
thresholds list-of-8-integers
Provides the leading edge discriminator thresholds for each
channel. See also lt below.
lt booleanIf true the leading edge discriminator fires when the data go below the threshold. If false (the default) the discriminator fires when the data go above the threshold.
Note that the discriminator is actually firmware that monitors the flash ADC values rather than an analog leading edge discriminator.
freerunning boolean
If true the module is always sampling
and only stops sampling when the stop input occurs
(see also stopdelay). If false
(the default), the module starts sampling when the
start input occurs and stops either on the stop or
when the requested number of samples has been acquired.
See also startdelay and samplesize.
usegroups bitmask
The FADC is organized as two channel groups. Each group
can be independently enabled or disabled. bitmask
is a mask of the enabled channels. The default value
0xf enables all four groups (8 channels).
id number
See subpacket below. If subpacketing
is enabled, the data from the digitizer is encapsulated
in a packet (size and Id). number will
be used as the Id for the packet. The default value is
0x3300.
subpacket boolean
If true (the default), the data from
the digitizer is encapsulated in a packet. The id of
the packet is set using the id option
above.
clock clock-selectorSets the sampling frequency for the FADC. The legal values are a specific set of text strings: 100Mhz, 50Mhz, 25Mhz, 12.5Mhz, 6.25Mhz, 3.125Mhz set specific frequencies while frontpanel indicates the clock will be a front panel input and p2 indicates the clock will come in on the defined uncommitted P2 backplane pin. The default value is 100Mhz.
samplesize sample-size-selectorSets the number of samples after which acquisition will stop in start stop mode if not explicitly stopped. Legal values are: 128K, 16K, 4K, 2K, 1K, 512, 256 and 128. The default value is 16K.