module create name v1x90 ?option...?
name config option1 value1 ?...?
name cget ?pattern?
name help
Provides support for the CAEN V1190 and V1290 multi-hit TDCs. If you are used to a common start or common stop TDC it is important that you set aside that model of thinking before using this device. Support for this TDC is provided for Trigger Matching mode. No support is provided for Continuous storagemode.
In trigger matching mode, a front panel trigger together with a trigger offset and window size, define a time window in which hits are accepted. The offset can be prior to the trigger or after the trigger time. It is important to note that the trigger is accepted by the TDC on the edge of its internal FPGA clock (25ns/tick) rather than at the resolution of the TDC. This means that if you need absolute trigger-relative timing you will need to split the trigger and digitize it as well so that it can be digitally subtracted from the hits (in analysis software) otherwise your time resolution will be limited to only 25ns.
The TDC is rather complex and I recommend you thoroughly understand the manual before proceeding.
base base-addressSets the base address of the module. This must match the address implied by the rotary switch settings on the module itself.
crate crate-numberSets the number of the VME crate in which the module is installed. This defaults to 0 which works for systems with a single VME crate.
vsn virtual-slotData from the TDC is identified by a virtual slot number. This is an 8 bit number (range 0-255) that should be unique across al TDCs and allows you to distinguish data from specific TDCs. The default value is 0.
termination termination-selectorControl bus termination can be any of three possible values: on the control bus is terminated off the control bus is not terminated. switch termination is determined by the position of the TERM switch on the module circuit board.
tagtriggertime booleanIf true the trigger time is included in the data. Note that this trigger time is only known to a time resolution of 25ns. The default value is true.
eclprogout output-selector
The module has an ECL output that can be programmed to
reflect several conditions. The output-selector
determines the condition that is reflected on the output pin.
Legal values are dataready, full, almostfull, or error.
windowwidth integerDetermines the number of clock ticks (25ns units) of the window in which hits are accepted. See the manual for the legal range of values.
offset integerDetermines the offset of the start of the window relative to the trigger latch time. This can be a negative (window opens prior to the trigger) or positive (window opens after the trigger) value. See the manual for the legal range of values.
extramargin integerThis parameter provides an extra time buffer for the matching window to make up for the fact that the matching window is only precise to the FPGA clock which runs a click every 25ns. The manual describes the range of legal values and refers to this parameter as the extra search margin
rejectmargin integer
In order to support matching windows that preceded the trigger,
hits are recorded in an internal buffer and only recorded
to the multi event buffer when a trigger occurs, at which time
the hits inside the window are transferred.
The rejectmargin determines the minimum
retention time of the hits.
subtractriggertime booleanIf true (the default), the trigger time is subtracted from te hit time. If false the trigger time is not subtracted from the hit tiems.
edgedetectmode edge-detect-selectorDetermines which edges of the signal are digitized. If leading is selected, the leading edge of the signal is digitizied. If trailing the trailing edge. if both both edges of the signal are digitized resulting in two times for each pusle. If pair, two time values are digitized for each hit. The leading edge time and the width of the pulse.
encapsulatetdc booleanIf true (the default) the data from each TDC chip in the module is encapsulated in a TDC header and trailer as defined by the module data format, if false these headers are omitted from the data.
maxhits max-hit-selectorDetermines the maximum number of hits that will be accepted by the TDC for an event. Note that this is across all channel. To further clarify, selecting a value of 1 means the entire module will only give you at most a single hit for each event.
Legal values are 1, 2, 4, 8, 16, 32, 64, 128 and unlimited.
individuallsb lsb-selectorDetermines the meaning of the least significant bit for a conversion time value. The legal values are: 25ps, 100ps, 200ps and 800ps. The default value is 100ps. Note that not all TDC models support all of these values. There is currently no checking done to ensure that you have chosen a legal value fro the module you are using. This value only is meaningful when the edge match mode is not pair.
pairleresolution pairleres-selectorWhen in pair mode determines the resolution of the arrival time of the leading edge. This can be one of 100ps, 200ps, 400ps, 800ps, 1600ps, 320ps, 6250ps or 12500ps
pairwidthresolution pairwidres-selectorWhen in pair mode, determines the resolution with which the width of the input puls is measured. This can be one of the following values: 100ps, 200ps, 400ps, 800ps, 1600ps, 3200ps, 6250ps, 12500ps, 25ns, 50ns, 100ns, 200ns, 400ns or 800ns.
deadtime dead-time-selector
In order to prevent digitization of signal reflection from the
input cables, once a hit is recorded, a channel will
remain insensitive to addtional hits for a programmable
dead time that is determined by this parameter.
Legal values of the dead-time-selector
are:
5ns, 10ns, 30ns and 100ns.